The present invention relates to improving data transmissions on a data bus and, more particularly, to reducing the time constant associated with the data bus during voltage transition periods.
Some data busses, such as inter-integrated circuit (I2C) busses, have limited capabilities due to high time constants associated With the data busses. The I2C bus has two conductors referred to as a clock signal line and a data signal line. The voltages of both of these lines are pulled high via pull up resistors connected to a voltage source. When a device uses the bus, the device pulls the voltages on the lines down in a preselected sequence to indicate that it is preparing to transmit data on the bus. Data is then transmitted via voltage transitions on the lines. When the device is finished using the data bus, the device releases the lines so that they may float or otherwise be pulled to high voltages in a preselected sequence by the pull up resistors in conjunction with the voltage source.
The voltages on the lines of an I2C bus float when they are not pulled to a low voltage. This floating is due to open collector devices connected to the lines. In order to assure that the lines float to a high voltage when they are not being pulled to a low voltage by a device connected to the lines, the lines are connected to a direct current power supply via pull up resistors.
If the voltages on the lines are not able to float high within a preselected period, the data bus will not operate properly. One problem that may occur is that devices connected to the data bus will not be signaled that the data bus is available for data transmission. Another problem that may occur is that voltage transitions that are meant to be representative of data transfers may be interpreted incorrectly. For example, if voltage transitions on the clock signal data line take too long to complete, data may not be properly transmitted on the data bus. The same may occur if voltage transitions on the data signal line take too long to complete. Furthermore, if the voltage transition from one line is slower than the other line, the aforementioned voltage transition sequences may not occur correctly, which will prevent data from being properly transmitted via the data bus.
One cause of an increase in the voltage transition time on the data bus is due to an increased time constant associated with the data bus. For example, if the capacitance associated with the data bus increases, the time constant associated with the data bus will increase. Accordingly, the above-described problems associated with excessive time for the voltage transitions may occur. In one embodiment of an I2C bus, the capacitance is limited to approximately 433 picofarads. Should the capacitance increase beyond this amount, the data bus may be rendered dysfunctional as described above.
Increases in capacitance occur for many reasons. One cause of an increase in capacitance is due to the addition of more or longer data lines. For example, if the data lines are long, their capacitance will increase, which will cause the time constant associated with the data bus to increase. Another cause of an increase in capacitance is due to the addition of devices to the data bus. All devices added to the data bus have an internal capacitance. As more devices are added to the data bus, their internal capacitance adds, which increases the time constant associated with the data bus.
The present invention is directed toward a device for reducing the time constant of a system having a conductor connected thereto as a voltage on the conductor transitions from a first voltage to a second voltage. The device may comprise a voltage comparator, an impedance, a switch, and a timer.
The voltage comparator may have an input that is operatively connected to the conductor. The voltage at the voltage comparator output is transitionable between a first voltage and a second voltage when the voltage of the conductor exceeds a first preselected voltage.
The switch may be operatively connected to the voltage comparator output and the impedance. The switch connects the impedance to the conductor when the switch is in a first switch state and disconnects the impedance from the conductor when the switch is in a second switch state. Accordingly, the time constant of the system is reduced when the switch is in the first switch state.
The timer may be operatively connected to the switch and the first voltage comparator. The timer is transitionable from a timer first state to a timer second state for a preselected period upon the transition of the voltage at the a voltage comparator output from the first voltage to the second voltage.
The first switch state occurs when the voltage at the first voltage comparator output transitions from the first voltage to the second voltage. The second switch state occurs when the timer transitions to the second timer state.